A (204,188) Reed-Solomon decoder using decomposed Euclidean algorithm

Full metadata record

DC Field	Value	Language
dc.contributor.author	Chang, HC	en_US
dc.contributor.author	Cheng, CY	en_US
dc.contributor.author	Tsai, SH	en_US
dc.contributor.author	Lee, CY	en_US
dc.date.accessioned	2014-12-08T15:27:05Z	-
dc.date.available	2014-12-08T15:27:05Z	-
dc.date.issued	2000	en_US
dc.identifier.isbn	0-7803-6475-9	en_US
dc.identifier.uri	http://hdl.handle.net/11536/19316	-
dc.description.abstract	A (204, 188) Reed-Solomon decoder for DVB application is presented. The RS decoder features an area-efficient Key Equation Solver using a novel decomposed Euclidean algorithm. We implement the RS decoder using 0.35 mum CMOS 1P4M standard cells, where the total gate count is about 16K similar to 17K. Test results show that the RS decoder chip can run up to 87MHz.	en_US
dc.language.iso	en_US	en_US
dc.title	A (204,188) Reed-Solomon decoder using decomposed Euclidean algorithm	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III	en_US
dc.citation.spage	262	en_US
dc.citation.epage	265	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000172099300061	-
Appears in Collections:	Conferences Paper