A (208,192;8) Reed-Solomon decoder for DVD application

Abstract

The Digital Versatile Disk (DVD) is an emerging standard to meet the ever increasing storage capacity requirement of future high quality video and audio applications. In this paper, we implement a (208, 192; 8) Reed-Solomon decoder for the DVD Reed-Solomon product code (RS-PC). We propose a new area-efficient architecture which uses only three finite field multipliers (FFMs) to implement the inversion-less Berlekamp-Massey algorithm. The error value evaluator employs an algorithm-based GF(2(m)) inverter instead of an inversion ROM-table. We implement the (208, 192; 8) Reed-Solomon decoder using a 0.6 mu m SPDM CMOS technology with an area of 12.35 mm(2) (core area 6.45 mm(2)). The chip can run at 16.67MHz, while the DVD requirement is 3.74MHz. A minor error was found in this first version which a corrected in the second version of the chip.