| 標題: | AN ON-CHIP ESD PROTECTION CIRCUIT WITH COMPLEMENTARY SCR STRUCTURES FOR SUBMICRON CMOS ICS |
| 作者: | KER, MD WU, CY JIANG, HC LEE, CY KO, J HSUE, P 電控工程研究所 Institute of Electrical and Control Engineering |
| 公開日期: | 1994 |
| URI: | http://hdl.handle.net/11536/20136 |
| ISBN: | 0-7803-2428-5 |
| 期刊: | PROCEEDINGS OF THE 37TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 |
| 起始頁: | 1145 |
| 結束頁: | 1148 |
| 顯示於類別： | 會議論文 |
- COMPLEMENTARY-SCR ESD PROTECTION CIRCUIT WITH INTERDIGITATED FINGER-TYPE LAYOUT FOR INPUT PADS OF SUBMICRON CMOS ICS / KER, MD;WU, CY
- A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's / Ker, MD;Chang, HH;Wu, CY
- Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI / Ker, MD;Wu, CY;Chang, HH
- SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes / Ker, MD;Hsu, KC
- Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection / Chen, Shih-Hung;Ker, Ming-Dou
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