AN ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER WITH LOW RATIO-SENSITIVITY AND GAIN-SENSITIVITY AND 4N-CLOCK CONVERSION CYCLE

Title:	AN ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER WITH LOW RATIO-SENSITIVITY AND GAIN-SENSITIVITY AND 4N-CLOCK CONVERSION CYCLE
Authors:	CHIN, SY WU, CY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
Issue Date:	1994
URI:	http://hdl.handle.net/11536/20188
ISBN:	0-7803-1915-X
Journal:	1994 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 5: LINEAR CIRCUITS AND SYSTEMS (LCS) - ANALOG SIGNAL PROCESSING (ASP)
Begin Page:	E325
End Page:	E328
Appears in Collections:	Conferences Paper