A 40 Gbps Optical Receiver Analog Front-End in 65 nm CMOS

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DC Field	Value	Language
dc.contributor.author	Chou, Shun-Tien	en_US
dc.contributor.author	Huang, Shih-Hao	en_US
dc.contributor.author	Hong, Zheng-Hao	en_US
dc.contributor.author	Chen, Wei-Zen	en_US
dc.date.accessioned	2014-12-08T15:30:06Z	-
dc.date.available	2014-12-08T15:30:06Z	-
dc.date.issued	2012	en_US
dc.identifier.isbn	978-1-4673-0219-7	en_US
dc.identifier.issn	0271-4302	en_US
dc.identifier.uri	http://hdl.handle.net/11536/21567	-
dc.description.abstract	A 40 Gbps optical receiver analog front end integrating a trans-impedance amplifier (TIA) and a limiting amplifier is presented. To achieve wide band operation, nested feedback TIA and interleaving post amplifier with split series-peaking are proposed in this design. This receiver provides the transimpedance of 92 dBOhm, input-referred noise of 14 pA/root Hz, -3dB bandwidth of 35 GHz, and 800mV(pp) differential output voltage swing. The total power dissipation is 168 mW from 1.2-V supply. Fabricated in a 65 nm CMOS technology, the chip size is 0.825mm(2).	en_US
dc.language.iso	en_US	en_US
dc.title	A 40 Gbps Optical Receiver Analog Front-End in 65 nm CMOS	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012)	en_US
dc.citation.spage	1736	en_US
dc.citation.epage	1739	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000316903701236	-
Appears in Collections:	Conferences Paper