Reliability of passivated P-type polycrystalline silicon thin film transistors

Abstract

We have used NH3, N2O and N-2 to passivate the traps in the grain boundaries of the p-type polycrystalline silicon thin film transistors (p-type poly-Si TFTs). Two different stress conditions, drain voltage V-d of -15V and -30V, have been applied to the poly-Si TFTs respectively while the gate voltage V-g were kept at -15V for both conditions and the stress time were 10 minutes at room temperature for all samples. The comparisons of I-V characteristics after stress with and without plasma passivations have been made, and the results indicated that the reliability will become worse for poly-Si TFTs after plasma passivations. (C) 2000 Elsevier Science Ltd. All rights reserved.