Title: | Fuzzy-based CMOS circuit partitioning in built-in current testing |
Authors: | Tseng, WD Wang, KC 資訊工程學系 Department of Computer Science |
Keywords: | CMOS;cost;partitioning;performance;test |
Issue Date: | 1-Mar-1999 |
Abstract: | We propose a fuzzy-based approach which pro,ides a soft threshold to determine the module size for CMOS circuit partitioning in built-in current testing (BICT). Experimental results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning in comparison with other approaches with a fixed threshold, and a better module size can thus he determined to reflect a change of circuit properties. |
URI: | http://dx.doi.org/10.1109/92.748207 http://hdl.handle.net/11536/31495 |
ISSN: | 1063-8210 |
DOI: | 10.1109/92.748207 |
Journal: | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
Volume: | 7 |
Issue: | 1 |
Begin Page: | 116 |
End Page: | 120 |
Appears in Collections: | Articles |
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