晶片—封裝—印刷電路板共同設計之演算法

Abstract

因應系統晶片(SoC)與系統封裝(SiP)等產品急遽增加的趨勢，晶片、封裝和印刷電路板的設計以及其間的訊號互動，兩者之複雜度均快速成長。典型的周邊打線(wire-bond)封裝方式將不復適用於現今大部份的設計；因此覆晶(flip-chip)封裝成為一個必然的選擇。然而，在傳統的覆晶封裝設計中，工程師通常利用手動的方式來安排關鍵的介面，包括：輸入⁄輸出(I/O)、連接凸塊(bump)及封裝接腳(pin-out)，這種方式在晶片—封裝—印刷電路板(chip-package-board)的共同設計過程中相當耗時且費工，所以總是造成產品上市時程(time-to-market)的延宕。針對上述的問題，本篇論文提出一系列自動化安排、規劃這些重要介面的方法，配合論文中所發展之同時且共同設計流程(concurrent codesign flow)，可大幅加速產品設計的時程。 本篇論文主要包含三個部份。首先，針對封裝—印刷電路板 (package-board)共同設計的工作，論文中提出了一個全新且非常有效率的方法，以自動安排覆晶封裝的接腳位置，來取代以往耗時、費工的手動設計方式。在此方法中，由於建構與擺置封裝接腳方塊(pin-block)的過程，可以同時考慮訊號完整性(signal integrity)、電源供應(power delivery)和可繞線度(routability)，因此我們的方法不但讓工程師在產品效能及成本之間做彈性的選擇與取捨，並且同時實現封裝尺寸的最小化。其次，為了最佳化接腳方塊的位置，本論文提出另一個規劃封裝接腳的演算法。此方法應用新的接腳方塊擺置表示法(placement representation)，在有區域限制式(range constraint)的情況下，利用隨機的方法(stochastic framework)達到最佳化的目的。實驗結果顯示，在安排封裝接腳時改善接腳方塊的位置，確實可使系統連線(system interconnect)得以最佳化。除了處理封裝—印刷電路板共同設計的問題外，論文在第三部份亦發展了晶片—封裝(chip-package)同時且共同設計流程。相較於其他文獻中的演算法，我們的晶片—封裝共同設計方法針對繞線交錯(net crossing)與線長差異(length deviation)等重要設計考量，執行初步的探索及研究，試圖使兩者在爾後的設計過程中均可達成最佳化。藉由設計特定的輸出入連接凸塊板(I/O-bump tile)，以及提出新穎的輸出入列(I/O-row)結構，論文中呈現了兩個啟發式方法(heuristic method)和一個指派演算法(assignment algorithm)，根據已知的封裝接腳位置安排輸入／輸出和連接凸塊。綜合上述的研究成果，我們完成了同時兼顧產品效能與成本的自動化晶片—封裝—印刷電路板共同規劃任務。

Due to the trend of more and more SoC and SiP projects, the complication in chip, package and board designs, and signal interactions thereof is increasing very rapidly. Typical peripheral wire-bond design will be inappropriate for most modern designs; therefore flip-chip package becomes an inevitable choice. However, engineers usually designate the key interfaces including I/Os, bumps and package pin-out (ballplan) by hands in conventional flip-chip designs. The chip-package-board co-planning process is indeed time-consuming and always postpones the time-to-market (TTM) of products. In response to the aforementioned issues, this dissertation proposes methodologies in planning those interfaces with concurrent codesign paradigm, thus speeding up the developing time dramatically. The dissertation contains three parts. First, we propose a novel and very efficient approach to automating pin-out designation in flip-chip BGA packaging for package-board codesign. The manual time-consuming codesign works can be replaced by proposed methodologies. Through considering signal integrity, power delivery, and routability in pin-block design, our frameworks provide trade-offs in signal performance and package cost while achieving the minimum package size. Second, we present a planning algorithm to optimize pin-block locations by using a new representation for pin-block placement, and defining range constraints in stochastic framework. The experimental results show that our algorithm optimizes the system interconnects during package pin-out planning. In addition to the package-board codesign, we develop a concurrent design flow for chip-package codesign in the third part. Comparing with the previous works, the methods in this part preliminarily provide the optimization study of net crossing and length deviation which are very critical requirements in chip-package codesign. By designing specific I/O-bump tiles and proposing an innovative I/O-row based scheme, two heuristic methods and one assignment algorithm are provided for package-aware I/O-bump planning. As a result, a chip-package-board co-planning automation attempt is accomplished for optimizing performance and design cost simultaneously.