| 標題: | THE EFFECT OF LAYOUT, SUBSTRATE WELL BIASES, AND TRIGGERING SOURCE LOCATION ON LATCHUP TRIGGERING CURRENTS IN BULK CMOS CIRCUITS |
| 作者: | YANG, YH WU, CY 交大名義發表 電控工程研究所 National Chiao Tung University Institute of Electrical and Control Engineering |
| 公開日期: | 1-Apr-1989 |
| URI: | http://hdl.handle.net/11536/4389 |
| ISSN: | 0038-1101 |
| 期刊: | SOLID-STATE ELECTRONICS |
| Volume: | 32 |
| Issue: | 4 |
| 起始頁: | 269 |
| 結束頁: | 279 |
| Appears in Collections: | Articles |
- Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology / Chen, SH;Ker, MD
- Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology / Ker, MD;Lo, WY
- Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product / Lin, IC;Huang, CY;Chao, CJ;Ker, MD
- Active Guard Ring to Improve Latch-Up Immunity / Tsai, Hui-Wen;Ker, Ming-Dou
- Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs / Hsu, Sheng-Fu;Ker, Ming-Dou
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