低電壓互補式金氧半製程下的類比電路設計與可靠度

Abstract

隨著電子科技的快速發展，電子產品不斷地要求輕、薄、短、小，使得積體電路(Integrated Circuit)可靠度(Reliability)的重要性與日俱增，許多應用更需透過奈米級先進製程來實現才能帶來性能上的突破。半導體製程的微縮化造成電晶體(Transistor)元件尺寸越來越小、閘極氧化層(Gate Oxide)也越來越薄、和操作電壓也越來越低，所帶來一些元件非理想特性也對類比電路產生了重大的影響，大大提高了類比積體電路設計難度，其中在低電壓的操作設計和越來越薄閘極氧化層問題最為嚴重，所以新型低電壓類比電路設計技術與閘極氧化層的可靠度對類比積體電路之影響是十分重要的研究主題。本論文提出了一個新型之低操作電壓能隙參考電壓源(Bandgap Reference)電路與適用於低操作電壓能隙參考電壓源電路之溫度曲率補償(Curvature Compensation)技術，並針對閘極氧化層可靠度對類比電路影響進行研究與分析，另外探討了在奈米互補式金氧半製程中閘極漏電流(Gate Tunneling Current)對鎖相迴路(PLL)之影響，最後針對低溫多晶矽製程(LTPS)中提出適用於玻璃基板上類比電路設計且具有臨界電壓(Threshold Voltage)補償功能之偏壓電路設計技術。 在第二章中，本論文提出了一個低操作電壓之能隙參考電壓源電路與一個適於低操作電壓隙參考電壓源電路之溫度曲率補償技術。該新型低操作電壓能隙參考電壓源電路，最低操作電壓為0.85伏特，在此操作電壓之下，溫度範圍從-10□C到120□C的條件下，能隙參考電壓源電路的輸出電壓之溫度係數(Temperature Coefficient)為58.1 ppm/□C，此外，也將提出適於低操作電壓能隙參考電壓源電路之新型溫度曲率補償技術，經由實際晶片實現與驗證，此新型溫度曲率補償技術可以在能隙參考電源電路在最低操作電壓為0.9伏特，在溫度範圍從0□C到100□C的條件下，能隙參考電壓源電路的輸出電壓之溫度係數可以達到19.5 ppm/□C。本論文所提出的一個新型低操作電壓能隙參考電壓源電路與一個適於低操作電壓能隙參考電壓源電路之新型溫度曲率補償之技術，已經在0.25微米互補式金氧半製程中實現並驗證。 半導體製程的微縮化造成電晶體元件尺寸越來越小、閘極氧化層也越來越薄，電晶體的閘極氧化層變得更為脆弱更容易遭受破壞，目前已有文獻針對閘極氧化層可靠度對數位與射頻積體電路影響進行分析與探討，可是在類比積體電路上仍未有深入的研究與分析。因此，在第三章中，針對閘極氧化層可靠度對類比電路影響進行研究與分析，針對有無堆疊結構之主動式負載共源級放大器(Common-Source Amplifier)和雙級式(Two Stage)與折疊式(Folded Cascade)運算放大器(Operational Amplifier)進行探討，分析閘極氧化層可靠度對類比電路的影響，並針對閘極氧化層軟式崩潰(Soft Breakdown)與閘極氧化層硬式崩潰(Hard Breakdown)對類比電路的影響作了詳細的分析。本論文所探討之測試電路已經在1伏130奈米互補式金氧半製程裡實現，並已在2.5伏的操作電壓環境下進行分析。 在低電壓互補式金氧半製程中為了使交換式電容電路(Switched- Capacitor Circuit)具有較大的輸入信號範圍與操作速度，因而在交換式電容電路中電晶體開關均會利用閘極升壓技術(Gate Bootstrapped Technique)來設計，可是此設計方式會使得電晶體開關之閘極氧化層跨壓超過正常操作電壓，長時間操作下會對電晶體開關之閘極氧化層產生破壞。在第四章中，本論文探討電晶體開關之閘極氧化層可靠度對交換式電容電路的影響。利用所提出的交換式電容測試電路來進行分析，包括在時域與頻域的波形變化，並針對閘極氧化層軟式崩潰與閘極氧化層硬式崩潰對交換式電容電路的影響作了詳細的分析。此測試電路已經在1.2伏130奈米互補式金氧半製程中驗證。 鎖相迴路是用來於晶片系統中產生一個精準時脈的電路，為了使鎖相迴路能夠穩定的操作，在鎖相迴路之迴路濾波電路(Loop Filter)中均需要一個很大之電容器，通常在晶片上，此電容主要是利用電晶體來實現。當使用奈米互補式金氧半製程來設計鎖相迴路時，因為越來越薄的閘極氧化層將會發生嚴重的閘極漏電流問題。因此，在第五章中，本論文探討電晶體電容之閘極漏電流問題對鎖相迴路的影響，分析鎖相迴路之時基抖動(Jitter)在時域上受電晶體閘極漏電流的影響。本論文所探討之二階鎖相迴路使用1伏90奈米互補式金氧半製程之元件模型進行模擬與分析。 顯示系統面板技術的發展，已可在面板基板上加入電子電路，擴張顯示器產業的應用領域。由於複晶矽薄膜電晶體較傳統用於薄膜電晶體顯示器面板之非晶矽薄膜電晶體有更大的載子遷移率(Mobility)、較大的驅動電流、較小的臨界電壓，所以可實現顯示器驅動電路的潛力。然而，目前在系統面板內建電路設計中，最難克服的一個重點，即為“元件的變動率(Variation)”，相同元件在不同面版上的元件特性可能會有高達~30%的變動。因此，在第六章中，本論文提出具有臨界電壓補償功能之偏壓電路設計技術，此技術可以大幅降低元件的變動對偏壓電路的影響，提高類比電路在玻璃基板上之可行性。本論文所提出之適用於玻璃基板上類比電路設計且具有臨界電壓補償功能之偏壓電路設計已經在8微米低溫複晶矽薄膜電晶體製程中實現並驗證。 本博士論文提出了一個新型之低操作電壓能隙參考電壓源電路與適用於低操作電壓能隙參考電壓源電路之溫度曲率補償技術，並針對閘極氧化層可靠度對類比電路影響進行研究與分析，另外探討了在奈米互補式金氧半製程中閘極漏電流對鎖相迴路之影響，最後針對低溫多晶矽製程中提出適用於玻璃基板上類比電路設計且具有臨界電壓補償功能之偏壓電路設計技術。所提出的電路已在實際晶片上成功驗証，並有相對應的國際會議論文、國際期刊論文發表。

Due to the growing popularity of electronic technology, the electronic products are continuously asked to reduce its weight, thickness, and volume. So, the reliability of analog integrated circuit is more and more important. Moreover, with the device dimensions of the integrated circuits scaling down, the operation voltage and gate-oxide thickness of device had also been reduced. However, the extra non-ideal effects of devices have great impact on analog integrated circuit to increase design difficulty, such as the lower operation voltage and thin gate oxide. So the new design technique in low-voltage analog integrated circuit and the impact of gate-oxide reliability on performances of analog circuits can be developed. The thinner gate oxide of device will cause the reliability problem in nanoscale analog integrated circuit. In this dissertation, a new sub-1-V CMOS bandgap reference and curvature-compensation technique for CMOS bandgap reference circuit with sub-1-V operation, the impact of gate-oxide reliability on CMOS analog amplifier, the impact of gate tunneling current on performances of phase locked loop, and the new gate bias voltage generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process are presented. There are seven chapters included in this dissertation. The new sub-1-V CMOS bandgap reference and curvature-compensation technique for CMOS bandgap reference circuit with sub-1-V operation are presented in Chapter 2. The new proposed CMOS bandgap reference without using low-threshold-voltage device can be operated with minimum supply voltage of 0.85 V and the temperature coefficient is 58.1 ppm/□C from -10 □C to 120 □C without laser trimming. The new sub-1-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic NPN and PNP BJT devices in CMOS process, is presented. The new proposed curvature-compensation technique for CMOS bandgap reference circuit with sub-1-V operation has with has been temperature coefficient of 19.5 ppm/°C from 0 °C to 100 °C under minimum supply voltage of 0.9 V without laser trimming. In general, the VLSI productions have lifetime of 10 years, but the thin gate-oxide thickness of the MOS transistor has many problems, such as gate-oxide breakdown, tunneling current, and hot carrier effect that will degrade the lifetime of the MOS transistor. Therefore, to improve the gate-oxide reliability of MOS transistor and to investigate the effect of gate-oxide breakdown on CMOS circuit performances will become more important in the nanometer CMOS technology. In Chapter 3, the influences of gate-oxide reliability on CMOS analog amplifier are investigated with CMOS common-source amplifiers with diode-connected active load, two-stage and folded-cascade operational amplifiers in a 130-nm low-voltage CMOS process. The test conditions of this work include the dc stress, ac stress with dc offset, and large-signal transition stress under different frequencies and signals. After overstresses, the small-signal parameters, such as small-signal gain, unity-gain frequency, phase margin, and output dc voltage levels, are measured. The impact of soft and hard gate-oxide breakdowns on CMOS analog amplifiers has been analyzed and discussed. The hard breakdown has more serious impact to the CMOS analog amplifiers. The MOS switch with bootstrapped technique is widely used in low-voltage switched-capacitor circuit. The switched-capacitor circuit with the bootstrapped technique could be a dangerous design approach in the nano-scale CMOS process due to the gate-oxide transient overstress. In Chapter 4, the impact of gate-oxide transient overstress on MOS switch in switched-capacitor circuit is investigated with the sample-and-hold amplifier in a 130-nm CMOS process. After overstress on the MOS switch of SHA with open-loop configuration, the circuit performances in time domain and frequency domain are measured to verify the impact of gate-oxide reliability on circuit performances. The oxide breakdown on switch device will degrade the performance of bootstrapped switch technique. In□ nanoscale CMOS technology, the thin gate oxide causes the large gate tunneling leakage. In Chapter 5, the influence of MOS capacitor, as loop filter, with gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated and analyzed. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter. Overview on the prior designs of gate tunneling leakage compensation technique to reduce the gate tunneling leakage on MOS capacitor as loop filter in PLL is provided in this work. Low-temperature poly-Si LTPS thin-film transistors (TFTs) have attracted a lot of attentions in the applications with the integrated on-panel peripheral circuits for active-matrix liquid crystal display (AMLCD) and active-matrix light emitting diodes (AMOLEDs). Recently, LTPS AMLCDs integrated with driving and control circuits on glass substrate have been realized in some portable systems, such as mobile phone, digital camera, notebook, etc. In the near future, the AMLCD fabricated in LTPS process is promising toward System-on-Panel (SoP) or System-on-Glass (SoG) applications, especially for achieving a compact, low-cost, and low-power display system. However, the poly-Si TFT device suffers from significant variation in its threshold voltage, owing to the nature of poly silicon crystal growth in LTPS process. In Chapter 6, a new proposed gate bias voltage generating technique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon LTPS thin-film transistors (TFTs) is proposed. The new proposed gate bias voltage generating circuit with threshold-voltage compensation has been successfully verified in a 8-□m LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5% under biasing voltage of 3 V. The new proposed gate bias voltage generating technique with threshold-voltage compensation enables the analog circuits to be integrated and implemented by LTPS process on glass substrate for active matrix LCD (AMLCD) panel. In summary, several design and reliability of analog circuits in low-voltage CMOS processes are presented in this dissertation. The proposed circuits have been implemented and verified in silicon chips. The proposed CMOS bandgap reference circuits, the impact of gate-oxide reliability on CMOS analog amplifiers, and the proposed gate bias voltage generating technique are very useful for the advanced nanoscale CMOS technology and SoP application, respectively.