共用緩衝記憶體交換器的容錯架構設計

Abstract

在本論文中,我們討論共用緩衝記憶交換器之容錯架構設計.原先由日立公 司設計的共用緩衝記憶交換器是以單鏈串列來完成共用記憶體,然而,如果 有一個記錄下一個封包位置產生錯誤,所有交換器的輸出端均會輸出原本 不屬於該輸出端的封包.根據我們的模擬,在均勻分佈 0.9 的承載量下,只 要花大約 80 封包的時間所有交換器的輸出端均會原本不屬於該輸出端的 封包.為了避免此錯誤擴散現象,我們提出兩種基於雙鏈串列的容錯架構設 計.這兩種方式分別是剷除與循序.根據我們的模擬,只要產生錯誤的比率 很低,循序方式所造成的效能降低與沒有錯誤產生的情形是相差無幾. In the thesis, we investigate the fault-tolerant architectures of Shared Buffer Memory Switch(SBMS). The original SBMS proposed by Hitachi Ltd is based on single linked list to attain buffer management. However, if there is one error in the address chain memory which record the address of the next cell in the SBMS, the erroneous situation will spread over all all links in the SBMS. From our simulation, if one error injected into one port under uniform traffic with load 0.9, all eight ports will output cells not belonging to the original ports in about 80 cell slot time. In order to prevent from the fault spread problem, we propose two double linked list based architectures to combat adress chain failure. These two methods are Flush and In-Seq schemes. According to our simulation, if the error injection rate is low, the performance of In-Seq scheme experiences slight degradation comapred with error free situation.