标题: | IDEA晶片设计 The Design of an IDEA Chip |
作者: | 陳奕任 Chen, Yen-Renn 張明峰 Ming-Feng Chang 資訊科學與工程研究所 |
关键字: | 加解密晶片;IDEA;data ciphering chip;IDEA |
公开日期: | 1995 |
摘要: | 随着电脑网路的普及化,在开放式的网路上传递资料的机会与日俱增 。为了保护这些在网路上传递的资料之私密性,加密是种可行的方式。但 随着高速磁碟和网路的发展,这些加密的演算法以软体方式进行,在速度 上无法满足一些应用程式在及时( real time ) 上的要求,而以硬体方式 进行已被证实可解决这个问题。在这篇论文中,我们就是描述以超大型积 体电路将IDEA加密演算法做硬体实现的方法。其中IDEA加密演算法是一个 在90年初期提出的新加密演算法,其设计规律适合以硬体实现,且最重要 的是安全性这几年下来已被广泛地接受。我们在设计上的特点包括:在 IDEA的每回合(round)中应用了4 个阶段(stage)的管线(pipeline)架构。 另外资料加密的动作和输入、输出也是以管线的方式执行。此外为了适用 于各种不同的应用和加强保密效果,四种区块加密的标准模式 ( ECB、 CBC、CFB、OFB)都有支援。预估我们这颗晶片完成后,所有资料的加密和 解密工作均可在单一的硬体单元上完成,并可使用于磁碟与高速网路之及 时加解密应用上。 Due the rapid development of the computer network, there have been more and more chances to transfer information in the open environment. Encryption is a practical method to protect the private secrets in such environment. However, encryption is often a computation-intensive task that can not be effectively performed by microprocessors. Specialized hardware is a solution to this problem. In this thesis, we describe the design of an IDEA chip. IDEA is a new cipher whose regular structure suitable to be implemented in hardware. Most importantly, it has been accepted widely in security. In our design, we adopt a four- stage pipelined architecture for each round of IDEA. The data input, data encryption and data output are also executed in a pipelining fashion. Additionally, for different applications, the four standard operation modes of block ciphers, ECB, CBC, CFB and OFB are supported. It is expected that the design can perform data encryption and data decryption in a single hardware unit after accomplished. The design can be applied to on-line encryp tion in high-speed network and disk applications. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT840392005 http://hdl.handle.net/11536/60345 |
显示于类别: | Thesis |