标题: 最大概度软性决策序列解码之律动矩阵架构实作探讨
A systolic-array implementation of maximum-likelihood soft-decision sequential decoding
作者: 钟兴明
Hsin-Ming Chung
陈伯宁
Po-Ning Chen
电信工程研究所
关键字: 序列解码;律动矩阵;sequential decoding
公开日期: 1998
摘要: 维特比 (Viterbi) 演算法虽然是最大概度解码演算法, 但是它只有在较短的固定长度(constraint length)时才能实现. 序列解码 (Sequential decoding) 演算法的复杂度虽然和固定长度无关, 但是它不能达到最大可靠度决策. 韩教授和陈教授提出的最大可靠度序列解码演算法 (MLSDA) 不但具有序列解码的优点, 同时它也是最大可靠度解码演算法. 根据最大可靠度序列解码演算法, 我们做解码器的实作探讨.
一般传统的序列解码搜寻方法是把所有资料放在记忆体中直接做排列, 而每次所须时间则视资料多寡而定. 为了维持固定的排序时间, 我们修正了优先排队演算法 (PESPQ) 来实现最大可靠度序列解码演算法. 这种作法虽然会增加设计的复杂度, 但是可以保证在固定时间内能得到最好的结果.
我们也提出一个序列解码的观点, 将1/2码视为2/4码 (3/6码), 即是在解码的过程中结合二 (三) 个输入位元成一个单位. 因此我们可以在VLSI的实作上得到一些好处例如解码速度, 但是也相对的增加半导体的数目. 为了减少半导体的数目, 我们使用多输入跃动排序演算法来完成2/4码 (3/6码) 的MLSDA. 根据模拟结果, 当半导体数量增加一半时解码速度可以增加一倍.
Viterbi algorithm is a maximum-likelihood-decoding algorithm, but it can only be implemented in short constraint length. Sequential decoding decoding is independent of constraint length but the decoding result is not always a maximum-likelihood decision. The MLSDA proposed by Han and Chen has the advantage of sequential decoding and it is also a maximum-likelihood-decoding algorithm. According to MLSDA, we implement a new convolutional code decoder using stacks.
The tranditional method for sorting the nodes serached in the sequential decoding is using a RAM to model a stack memory, and the sorting time is not a constant duration. In order to fix this shortage, we modify the priority queue algorithms (PESPQ) to implement MLSDA. Although the priority queue module is more complex than the stack memory, it can deliver the best node in a constant duration.
All 1/2 convolutional codes may be treated as an equivalent 2/4 (3/6) codes during the decoding phase if we combine two (three) input bits as one unit. Consequently, we might have some advantage in VLSI implementation such as decoding speed; however, the gate counts of decoder will be increased. In order to reduce the number of gate counts we modify a multiple-inputs systolic queue algorithm to implement MLSDA for 2/4 (3/6) codes. As the simulation shown, the decoding speed may be double faster for (2/4) while the gate counts increase half.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT870435047
http://hdl.handle.net/11536/64506
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