完整后设资料纪录
DC 栏位 | 值 | 语言 |
---|---|---|
dc.contributor.author | 郑键桦 | en_US |
dc.contributor.author | Chein-Hua Cheng | en_US |
dc.contributor.author | 吴锦川 | en_US |
dc.contributor.author | Jiin-Chuan Wu | en_US |
dc.date.accessioned | 2014-12-12T02:25:37Z | - |
dc.date.available | 2014-12-12T02:25:37Z | - |
dc.date.issued | 2004 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT009211644 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/67224 | - |
dc.description.abstract | 随着积体电路制程技术的日新月异,处理器的运算速度愈来愈快,单位时间内处理的资料量也日益增多,通常,传输介面的电路所能达到的单位时间最大传输量往往是整体系统速度的关键限制,因此,本篇论文是描述一个应用于高速串列数位影像传输介面,使用低摆幅差动讯号传输之传送器的设计,并致力于设计此传送器之资料传输速度操作在 2Gbps 。 传送器由一个四相位锁相回路、虚拟随机位元串列产生器、二对一多工器和一拥有预先加强电路设计之输出驱动器所组成,其中,四相位锁相回路的输入频率为125MHz,输出为四个相位 平均分布且频率同为1GHz的时脉讯号,所包含的电路有相位/频率侦测器、电荷帮浦、回路滤波器、两级差动压控振荡器和一个除八的除频器。此锁相回路所产生的平均分布时脉提供给虚拟随机位元串列产生器和二对一多工器,并将一组并列资料转为串列输出,再经由输出驱动器并搭配预先加强电路,来增加传送资料位元转变期间所需的电流量,最后,将此串列资料传送至传输线上,即完成整个传送器的设计。 此传送器采用 TSMC 0.35μm 2P4M CMOS制程技术实现,当锁相回路输入时脉为66.67MHz时,传送器能正常传送出1066.67Mbps的串列资料。 | zh_TW |
dc.description.abstract | As the advancement of IC fabrication technology, the operation of processors has sped up. The amounts of data processed in each unit time become larger and larger as time goes by. For most of time, the key limitation of a whole system is the maximum data amounts of the transmission interface circuit transmitted in each unit time. Therefore, the thesis describes the design of a transmitter for a high-speed serial digital display interface by RSDS technique. We have devoted to design the data rate of the transmitter at 2Gbps. The transmitter is composed of a four-phase PLL, PRBS circuits, 2-1 multiplexers and an output data driver with a pre-emphasis circuit. Among these devices, the input frequency of the four-phase PLL is 125MHz; it outputs four uniformly distributed clocks with 1 GHz frequency. The PLL comprises a Phase/Frequency Detector, a Charge Pump, a Loop Filter, a two-stage differential VCO and a divided-by-eight divider. It offers the PRBS and the 2-1 multiplexer with four uniformly distributed clocks to convert parallel pseudo-data into serial stream. Then, the serial data is transmitted by an output data driver with the pre-emphasis circuit. The pre-emphasis circuit is designed to increase the current during the data transition. In the end, the transmitter drives the serial data onto the transmission bus. The transmitter is implemented in the TSMC 0.35μm 2P4M CMOS process. When the input reference frequency is 66.67MHz, the transmitter can transmit serial data at 1066.67Mbps successfully. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 低摆幅差动讯号传输 | zh_TW |
dc.subject | 传送器 | zh_TW |
dc.subject | RSDS | en_US |
dc.subject | Transmitter | en_US |
dc.title | 2Gbps 低摆幅差动讯号传输之传送器 | zh_TW |
dc.title | A 2Gbps Reduced Swing Differential Signaling (RSDS) Transmitter | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 电子研究所 | zh_TW |
显示于类别: | Thesis |
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