應用於數位電視廣播系統之通道等化器設計

Abstract

數位電視的發展為未來一大趨勢，在本論文中，我門將會介紹通道估測演算法以及在2005年6月，我們使用0.18微米製程實現了數位電視廣播系統基頻接收器的晶片設計。系統架構設計是根據歐規數位電視地面廣播系統的規格，以及考量通道非理想特性狀況。我們提出可適應性調整估測器的權重係數在時變通道中可達到降低雜訊干擾的效應。此外，通道響應使用散佈領航碼作二維通道響應的內插，我們分析多種多項式內插方法於不同通道下的效能。在硬體架構下，複數除法器佔了通道等化器大部分的硬體花費以及功率消耗，所以此處我們提出複數除法器的改善架構，在此架構可以有效率的降低硬體花費已及功率消耗。可節省原本90.5%的硬體花費以及59.9%的功率花費。

In this thesis, we introduce the channel estimation algorithm for DVB-T/H system, and COFDM basedband receiver chip for DVB-T/H applications. This chip is implemented with 0.18μm cell library and tapped out in Jun. 2005. The architecture is established according to the standard and several channel impairments. We propose the adaptive channel estimator for pilot signal which can average out the noise effects under portable environments. Furthermore, the channel response is estimated by means of two-dimension interpolation of scattered pilots. We analyze several polynomial interpolation methods under channels specified by standards. In architecture part, we can find the complex division is dominant the equalizer in cost and power. So we proposed the improved architecture for simplified the division architecture which hardware can be saved by 90.5% and power saved by 59.9% in divider itself.