在佈局階段時同時對緩衝器與正反器做放置規畫以及電壓下降的最小化

Abstract

隨著製程的進程，我們知道互連線已經是決定整個電路的效率以及複雜度最重要的因素。 緩衝器放置是一種對於改善互連線非常有效率的技術之一。 在佈局階段做緩衝器的放置時，通常會將緩衝器集結在一個區域，這樣有可能會因為額外電流而造成電壓下降過大。另一方面，隨著晶片愈來愈大，操作頻率愈來愈高，使得很多的全域訊號需要好多個週期才跨過整個晶片到達目的地。這使得我們需要把互連線管線化。 我們提出了一種可以在佈局階段做互連線的管線化並且在放置緩衝器以及正反器時，我們也會避免發生電壓下降過大的問題。由實驗結果來看，我們的方法可以得到低延遲的系統，且不會發生任何電壓下降過大的問題。

As the technology scales, it is well known that interconnect has become the dominant factor in determining the overall circuit performance and complexity. Buffer insertion is one of a very effective and useful techniques to improve the interconnect performance. The buffer insertion during floorplan stage usually clusters buffers in a region to minimize the area overhead, which may cause additional current and have the IR-drop violation. On the other hand, in complex digital system with relatively large die areas operating at very high frequencies, many global signals traveling across the chip need several clock cycles to reach their destinations, thus requiring the adoption of pipelined interconnects. We propose a methodology to pipeline interconnect during the floorplan stage and consider the IR-drop during the planning of buffers and flip-flops. The experimental results show our method can get a low system latency and without any IR-drop violation.