| Title: | E-Home核心技術之研究---子計畫五晶片上匯流排之架構設計及效能分析技術(I) Technologies on Architecture Design and Performance Analysis of On-Chip Bus(I) |
| Authors: | 黃俊達 Huang Juinn-Dar 交通大學電子工程系 |
| Issue Date: | 2004 |
| Gov't Doc #: | NSC93-2220-E009-029 |
| URI: | http://hdl.handle.net/11536/91118 https://www.grb.gov.tw/search/planDetail?id=1030986&docId=196434 |
| Appears in Collections: | Research Plans |
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