| Title: | 射頻電路系統前瞻測試技術開發(I) Advanced Test Technology Development for RF Circuits and Systems (I) |
| Authors: | 蘇朝琴 SU CHAU-CHIN 國立交通大學電機與控制工程學系 |
| Issue Date: | 2003 |
| Gov't Doc #: | NSC92-2218-E009-012 |
| URI: | http://hdl.handle.net/11536/91781 https://www.grb.gov.tw/search/planDetail?id=874721&docId=167675 |
| Appears in Collections: | Research Plans |
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- 射頻電路系統前瞻測試技術開發(II) / 蘇朝琴;SU CHAU-CHIN
- 射頻電路系統前瞻測試技術開發(III) / 蘇朝琴;SU CHAU-CHIN
- 奈米CMOS之高性能類比數位混合信號關鍵電路設計技術---子計畫二：極低寄生電容之靜電放電防護技術以應用於超高速/超高頻積體電路 / 柯明道;KER MING-DOU
- Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology / Lin, Chun-Yu;Chu, Li-Wei;Tsai, Shiang-Yu;Ker, Ming-Dou
- ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process / Lin, Chun-Yu;Chu, Li-Wei;Ker, Ming-Dou
- Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies / Ker, Ming-Dou;Lin, Chun-Yu;Hsiao, Yuan-Wen
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