| 標題: | BiCMOS低電壓積體電路設計 Bicmos Low-Voltage Integrated Circuit Design |
| 作者: | 吳介琮 WU JIEH-TSORNG 國立交通大學電子工程研究所 |
| 公開日期: | 1995 |
| 官方說明文件#: | NSC84-2622-E009-008 |
| URI: | http://hdl.handle.net/11536/96754 https://www.grb.gov.tw/search/planDetail?id=150264&docId=24762 |
| Appears in Collections: | Research Plans |
- BiCMOS低電壓積體電路設計---產學合作計畫(II) / 吳介琮;WU JIEH-TSORNG
- 新型靜態與動態雙載子互補式金氧半邏輯電路之設計與分析及其在低電壓超大型積體電路之應用 / 曾玉光;Tseng, Yuh-Kuang;吳重雨;Prof. Chung-Yu Wu
- Bipolar bootstrapped multi-emitter BiCMOS ((BM)-M-2-BiCMOS) logic for low-voltage applications / Wu, CY;Tseng, YK
- A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications / Tseng, YK;Wu, CY
- A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications / Tseng, YK;Wu, CY
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