| Title: | 資料路徑合成多重輸出入埠記憶體分配埠使用率研究 Research on Ports Utilization for Multiport Memories in Allocation in Data Path Synthesis |
| Authors: | 蕭培墉 HSIAO PEI-YUNG 國立交通大學資訊科學研究所 |
| Issue Date: | 1995 |
| Gov't Doc #: | NSC84-2213-E009-017 |
| URI: | http://hdl.handle.net/11536/96762 https://www.grb.gov.tw/search/planDetail?id=160927&docId=26765 |
| Appears in Collections: | Research Plans |
- 資料路徑合成中多重輸出入埠記憶體分配問題對埠使用率的提昇 / 張人祺;Jen-Chi Chang;蕭培墉;Dr. Pei-Yung Hsiao
- Memory system design in superscalar processing / Lu, NP;Chung, CP
- BRAM Efficient Multi-ported Memory on FPGA / Lin, Jiun-Liang;Lai, Bo-Cheng Charles
- Memory system design in superscalar processing / Lu, NP;Chung, CP
- Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors / Wang, Dao-Ping;Lin, Hon-Jarn;Chuang, Ching-Te;Hwang, Wei
- Efficient Designs of Multiported Memory on FPGA / Lai, Bo-Cheng Charles;Lin, Jiun-Liang
- MULTI-PORT SRAM WITH SHARED WRITE BIT-LINE ARCHITECTURE AND SELECTIVE READ PATH FOR LOW POWER OPERATION / HWANG Wei;WANG Dao-Ping
Loading...