瀏覽 的方式： 作者 KER, MD
顯示 1 到 8 筆資料，總共 8 筆
| 公開日期 | 標題 | 作者 |
| 1-一月-1994 | CMOS ON-CHIP ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT USING 4-SCR STRUCTURES WITH LOW ESD-TRIGGER VOLTAGE | KER, MD; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1995 | Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's | KER, MD; WU, CY; CHANG, HH; CHENG, T; WU, TS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-七月-1995 | COMPLEMENTARY-SCR ESD PROTECTION CIRCUIT WITH INTERDIGITATED FINGER-TYPE LAYOUT FOR INPUT PADS OF SUBMICRON CMOS ICS | KER, MD; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-六月-1995 | MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .1. THEORETICAL DERIVATION | KER, MD; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-六月-1995 | MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .2. QUANTITATIVE-EVALUATION | KER, MD; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-三月-1992 | A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSI | WU, CY; KER, MD; LEE, CY; KO, J; 電控工程研究所; Institute of Electrical and Control Engineering |
| 1994 | AN ON-CHIP ESD PROTECTION CIRCUIT WITH COMPLEMENTARY SCR STRUCTURES FOR SUBMICRON CMOS ICS | KER, MD; WU, CY; JIANG, HC; LEE, CY; KO, J; HSUE, P; 電控工程研究所; Institute of Electrical and Control Engineering |
| 1-二月-1994 | TRANSIENT ANALYSIS OF SUBMICRON CMOS LATCHUP WITH A PHYSICAL CRITERION | KER, MD; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
