瀏覽 的方式： 作者 Liang, BS
顯示 1 到 9 筆資料，總共 9 筆
| 公開日期 | 標題 | 作者 |
| 1997 | An area and time efficient adder for multiple additions with different word-length | Liang, BS; Nieh, YC; Jen, CW; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics |
| 1-五月-2002 | Base model transmission for 3D graphics in a network environment | Liang, BS; Jen, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-八月-2000 | Computation-effective 3-D graphics rendering architecture for embedded multimedia system | Liang, BS; Jen, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-一月-2000 | Computation-effective 3-D graphics rendering architecture for embedded multimedia system | Liang, BS; Jen, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1997 | Enacting a software development process | Chen, MF; Liang, BS; Lin, RJR; Wang, FJ; 交大名義發表; 資訊工程學系; National Chiao Tung University; Department of Computer Science |
| 1995 | A hardware-efficient architecture for 3-D graphics processor | Liang, BS; Nieh, YC; Niou, YP; Jen, CW; Chuang, G; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics |
| 1-九月-2002 | Index rendering: Hardware-efficient architecture for 3-D graphics in multimedia system | Liang, BS; Lee, YC; Yeh, WC; Jen, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-五月-2000 | A project model for software development | Liang, BS; Chen, JN; Wang, FJ; 資訊科學與工程研究所; Institute of Computer Science and Engineering |
| 25-十月-2001 | Speed up of rendering pipeline by deferred lighting and triple queue structure | Liang, BS; Jen, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
