1. You are Here：

Browsing by Author Lo, WY

Jump to: 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
or enter first few letters:  
Showing results 1 to 14 of 14
Issue DateTitleAuthor(s)
1-Mar-2004Abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing nonconnected ballsLo, WY; Ker, MD; 電機學院; College of Electrical and Computer Engineering
1-Sep-2003Analysis and prevention on NC-ball induced ESD damages in a 683-pin BGA packaged chipset ICLo, WY; Ker, MD; 電機學院; College of Electrical and Computer Engineering
2001Compact layout rule extraction for latchup prevention in a 0.25-mu m shallow-trench-isolation silicided bulk CMOS processKer, MD; Lo, WY; Chen, TY; Tang, H; Chen, SS; Wang, MC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Apr-2000Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS processKer, MD; Lo, WY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-May-2005ESD implantations for on-chip ESD protection with layout consideration in 0.18-mu m salicided CMOS technologyKer, MD; Chuang, CH; Lo, WY; 電機學院; College of Electrical and Computer Engineering
1-Jan-2002ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustnessKer, MD; Lo, WY; Lee, CM; Chen, CP; Kao, HS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustnessKer, MD; Lo, WY; Lee, CM; Chen, CP; Kao, HS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS processKer, MD; Chuang, CH; Hsu, KC; Lo, WY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
21-Mar-2002Exact solution of inventory replenishment policy for a linear trend in demand - two-equation modelLo, WY; Tsai, CH; Li, RK; 工業工程與管理學系; Department of Industrial Engineering and Management
2001Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-mu m salicided CMOS processKer, MD; Chuang, CH; Lo, WY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2004Low-voltage-triggered PNP devices for ESD protection design in mixed-voltage I/O interface with over-VDD and under-VSS signal levelsKer, MD; Chang, WJ; Lo, WY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2006A method for calibrating a motorized object rigHuang, PH; Tsai, YP; Lo, WY; Shih, SW; Chen, CS; Hung, YP; 資訊工程學系; Department of Computer Science
1-May-2003Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technologyKer, MD; Lo, WY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2000New diode string design with very low leakage current for using in power supply ESD clamp circuitsKer, MD; Lo, WY; Chang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
Showing results 1 to 14 of 14