Browsing by Author YANG, YH
Showing results 1 to 5 of 5
| Issue Date | Title | Author(s) |
| 1-Oct-1989 | ANALYSIS AND MODELING OF INITIAL DELAY TIME AND ITS IMPACT ON PROPAGATION DELAY OF CMOS LOGIC GATES | YANG, YH; WU, CY; 電子工程學系及電子研究所; 電控工程研究所; Department of Electronics Engineering and Institute of Electronics; Institute of Electrical and Control Engineering |
| 1-Apr-1989 | THE EFFECT OF LAYOUT, SUBSTRATE WELL BIASES, AND TRIGGERING SOURCE LOCATION ON LATCHUP TRIGGERING CURRENTS IN BULK CMOS CIRCUITS | YANG, YH; WU, CY; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering |
| 1985 | A NEW APPROACH TO MODEL CMOS LATCHUP | WU, CY; YANG, YH; CHANG, C; CHANG, CC; 工學院; College of Engineering |
| 1-Jul-1989 | A NEW CRITERION FOR TRANSIENT LATCHUP ANALYSIS IN BULK CMOS | YANG, YH; WU, CY; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering |
| 1-May-1988 | A NEW METHOD FOR DETERMINING THE TERMINAL SERIES RESISTANCES AND HIGH-INJECTION COEFFICIENT OF BIPOLAR-TRANSISTORS IN CMOS INTEGRATED-CIRCUITS FOR COMPUTER-AIDED CIRCUIT MODELING | YANG, YH; WU, CY; CHEN, WY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
