Title: An efficient heterogeneous tree multiplexer synthesis technique
Authors: Huang, HW
Wang, CY
Jou, JY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: capacitance;modeling;optimization;simulation;transistor sizing
Issue Date: 1-Oct-2005
Abstract: In this paper, a novel strategy for designing the heterogeneous tree multiplexer is proposed. The authors build the multiplexer delay model by curve fitting and then formulate the heterogeneous tree multiplexer design problem as a special type of optimization problem called mixed-integer nonlinear programming (MINLP). A new design parameter, the switch size in each stage, is introduced to improve the speed of the heterogeneous tree multiplexer. The proposed strategy can determine the multiplexer architecture and the switch size in each stage simultaneously. Three optimization methods are provided to synthesize the heterogeneous tree multiplexer according to the design specifications.
URI: http://dx.doi.org/10.1109/TCAD.2005.852032
http://hdl.handle.net/11536/13244
ISSN: 0278-0070
DOI: 10.1109/TCAD.2005.852032
Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume: 24
Issue: 10
Begin Page: 1622
End Page: 1629
Appears in Collections:Articles


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