Title: | Speed up of rendering pipeline by deferred lighting and triple queue structure |
Authors: | Liang, BS Jen, CW 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
Issue Date: | 25-Oct-2001 |
Abstract: | Redundant operations and stalls prevent a rendering pipeline from full-speed operation. To speed up the rendering pipeline, a triple queue structure is proposed to smooth the pipeline and to obtain benefit from deferred lighting. The results of cycle-accurate simulation show that the proposed structure can reduce rendering cycles to 52.9% in small size queues. |
URI: | http://dx.doi.org/10.1049/el:20010901 http://hdl.handle.net/11536/29335 |
ISSN: | 0013-5194 |
DOI: | 10.1049/el:20010901 |
Journal: | ELECTRONICS LETTERS |
Volume: | 37 |
Issue: | 22 |
Begin Page: | 1332 |
End Page: | 1333 |
Appears in Collections: | Articles |
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