應用參數化閉合型式並考慮時序相關性的統計型靜態時序分析於軟性錯誤率分析

Abstract

對於屬於次微米世代的CMOS 設計，由於製程變異，軟性錯誤的統計特性變得更為複雜。製程變異使得軟性錯誤的行為有極大的不確定性，因此要精準地估計電路的軟性錯誤，統計的方法是不可或缺的。然而，不論現有用於軟性錯誤架構的方法是什麼，這些方法通常需要在效率與準確度之間作取捨。因此在這篇論文，我們提出以一次標準式為基礎的邏輯閘單元模型，以降低時間耗損。在假設所有製程變異的參數皆為常態分佈的前提下，這些被推導成閉合形式的單元模型是精準的。根據這些模型，可以用類似區塊基準統計性時序分析法去分析統計性軟性錯誤。實驗結果展示了提出的模型只有很小的誤差並且證明了我們的方法可以極具效率地估計電路上的統計性軟性錯誤，而且對比SPICE 模擬出的結果是足夠準確的。

For CMOS designs in the deep submicron era, statistical methods are essential to accurately estimate circuit SER under process variations, which lead to significant uncertainty in behavior of soft errors. Due to process variations, a number of statistical natures of soft errors become more sophisticated than their static one. However, regardless of the methods used in current statistical SER (SSER) frameworks are, they usually require the tradeoff of accuracy and efficiency. In this work, we present accurate cell models based on a first-order-canonical form to reduce timing cost, and upon which, SSERs can be analyzed similarly to block-based SSTA. These cell models are derived in closed-form and precise under the assumption of normal distribution of process parameters. Experimental results show that the errors of proposed models are small and our approach is highly efficient for estimating circuit SSERs with reasonable accuracy when compared to SPICE simulation.