完整後設資料紀錄
DC 欄位語言
dc.contributor.author沈金發en_US
dc.contributor.authorChin-fa shenen_US
dc.contributor.author高曜煌en_US
dc.contributor.authorYao-Huang Kaoen_US
dc.date.accessioned2014-12-12T02:19:50Z-
dc.date.available2014-12-12T02:19:50Z-
dc.date.issued2006en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009167552en_US
dc.identifier.urihttp://hdl.handle.net/11536/63702-
dc.description.abstract中 文 摘 要 本論文研製之內建測試機制的衛星定位接收機前端電路設計是在敘述如何快速、輕鬆的設計RF IC(Radio frequency integrator circuit)[1]。快速、輕鬆的設計RF IC,一直是RF IC設計者期望的工作環境。但是設計RF IC傳統上就是很艱困、繁瑣的工作,因此想要輕鬆的設計RF IC就必須把設計的困難度降低才行,(不過規格是不能放寬的)。因此我們想:若設計出許多規格,然後再從中挑選一個那不就達到目的了嗎?當然要實現這個想法,也要有方法才不會弄巧成拙。因此本文在此推薦了一個RF IC的設計方法,讓RF IC設計者,能夠快速且輕鬆的設計RF IC。在此我們藉製作GPS Receiver(Global Positioning System) [2]來說明此RF IC的設計方法。 首先在設計VCO時我們內建了數個頻率範圍切換裝置,來克服頻率的不準度。並降低了KVCO之值,換句話說我們除了克服頻率的不準度外亦兼具改善了相當程度的電源引起之相位雜訊。 我們更在RF IC內部的VCO(Voltage control oscillator),內建了一組輸出電路,使得VCO的輸出,能夠被獨立的量測,因此之故它的性能亦可以單獨的被評估。舉一個例子來說,我們可以來評估它的輸出振幅大小和相位雜訊等等--------。 接著,我們在設計Crystal OSC時內建了偏壓電流選擇機制,來權衡耗電流和起振與否的問題。故此電流選擇機制,讓我們可以擁有更大的設計誤差,當然設計速度也提升了。 在設計Front end時我們亦特地在LNA及MIXER之內加了電流選擇裝置,使得LNA及MIXER的偏壓可以被手動改變。同樣的,有了這個電流選擇裝置後,我們將不再被規格綁緊了。換句話說,設計的困難度降低了。 本文使用了台灣積體電路公司(TSMC)的CMOS 0.25um製程,來設計並製造這顆“內建測試機制的衛星定位接收機”。目前此晶片已量測完成,量測結果是:RF IC感度=-94dBm@(S+N)/N=20dB。它的電源電壓為3.0V,耗電流為50mA。建立此設計方法之後,接著我們未來將以減少耗電流及提升感度為職志。zh_TW
dc.description.abstractABSTRACT A procedure is easy to design RF IC. RF IC designer wish own environment. But tradition design method is very difficult. At this paper we recommend a method to more easy design RF IC which for RF IC designer, for above reason. We building the GPS Receiver RF IC to present this recommend method. First, we build the frequency selector in VCO for Local Oscillator. So we have larger frequency range to overcome the IC device non-ideal and improve the phase noise from power supply induce. Next, we build the Output port for VCO. Then our VCO can be measurement for power level and frequency and phase noise. Third, we build in the current bias selector for crystal oscillator. Therefore, we can tread-off between current consumption and oscillation start time. Fourth, we build in the current bias selector for LNA and MIXER. Similar above we can tread-off current consumption and performance for LNA 、 MIXER (we call :FRONT-END). We have the above some mechanism then RF IC design become not difficult. There are we recommend RF IC design method by make GPS Receiver RF IC. We use 0.25um CMOS process of TSMC Corporation to design and make this GPS receiver RF IC. This RF IC power supply =3.0V, current consumption about 40 mA and it receiver sensitivity =-94dBm@(S+N)/N=20dB. After set up this method, we will do the reduce consumption current and improve the receiver sensitivity.en_US
dc.language.isozh_TWen_US
dc.subject測試機制zh_TW
dc.subject衛星定位接收機zh_TW
dc.subject電路設計zh_TW
dc.subject接收機zh_TW
dc.subject積體電路zh_TW
dc.subject射頻zh_TW
dc.subject高頻zh_TW
dc.subjectGPS Receiveren_US
dc.subjectReceiveren_US
dc.subjectRF ICen_US
dc.subjectBuilt In Test Modeen_US
dc.subjectVCOen_US
dc.subjectLNAen_US
dc.subjectMIXERen_US
dc.subjectOscillatoren_US
dc.title內建測試機制的衛星定位接收機前端電路設計zh_TW
dc.titleFront End Design With Built In Test Mode for GPS Receiveren_US
dc.typeThesisen_US
dc.contributor.department電機學院電信學程zh_TW
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