高速除頻電路與正交相位振盪器之設計

Abstract

本論文實作部分包含高速除頻電路與正交相位振盪器的設計。利用GCT 2.0 um InGap/GaAs HBT及TSMC 0.35μm SiGe BiCMOS之製程，在除頻電路方面實現了：(1)可操作在2~7.4GHz的靜態除頻電路；(2)可操作在2~11GHz的動態除頻電路；(3)可操作在6~9.7GHz的超動態除頻電路；(4)可操作在9.636~10.246GHz的注鎖型除頻電路；(5)可操作在7~27GHz的回復型除頻電路；(6)可操作0.25~3.8GHz的÷4/5電路；以上電路除了頻率不同外還有個別的優缺點，可依系統的需求選擇使用，詳細的說明將在本文中深入探討。在正交相位振盪器方面，實現了疊接耦合式和二階諧波耦合的架構，兩架構的相位雜訊和相位誤差互有優劣，可依收發機的規格要求擇優使用。此外在振盪器的設計上也提出了新的架構，預期會有不錯的電路特性表現。

This thesis presents the design of high speed frequency dividers and quadrature voltage controlled oscillators. First, we use GCT 2.0 um InGap/GaAs HBT and TSMC 0.35μm SiGe BiCMOS processes to implement the two kinds of circuits. In frequency divider circuits, have implemented several structures as follower：(1)Static frequency divider can operate from 2 to 7.4GHz. (2)Dynamic frequency divider can operate from 2 to 11GHz. (3)Superdynamic frequency divider can operate from 6 to 9.7GHz. (4)Injection locked frequency divider can operate from 9.636 to 10.246GHz. (5)Regenerative frequency divider can operate from 7 to 27GHz, and (6)Dual modulus frequency divider(÷4/5) can operate from 0.25 to 3.8GHz. Those circuits have particular characteristics and can be chosen to fit the specs of the system. The detail expansions will be discussed in the following chapters. Also, the realization of top-series and superharmonic coupling quadrature VCOs are shown in this thesis. One has a better phase noise than the other, but a worse phase error than the other. Each topology can be used in a transceiver that has different requirements of phase noise and phase error. Finally, a new structure of VCO is presented. Depending on the theories and simulations, the performance of the circuit might be better than the others.