以柵狀最小值-最大值演算法實現之 2.56 Gb/s 非二進位低密度同位元檢查碼解碼器架構

Abstract

由低密度同位元檢查碼衍伸而來的非二進位低密度同位元檢查碼，不僅具有極佳的錯誤更正能力及抵抗連續錯誤能力，並且相較於二進位碼有更低的繞線複雜度。然而，複雜的運算以及大量的記憶體需求，是其硬體實現上急需克服的問題與挑戰。在此論文，我們提出一個以改進柵狀最大值-最小值演算法實現高硬體效率及能量效率的非二進位低密度同位檢查碼解法器。改進柵狀最大值-最小值演算法因硬體共用而有低硬體複雜度，且我們藉由消除冗餘時脈週期顯著提升吞吐量。應用可以加速收斂速度的分層解碼架構及適合的建碼方法，儲存使用量也會下降。此外，使用無停止的管線化架構可以達到高的吞吐量。我們實現1063k邏輯閘的解碼器其包含測試考量的面積為2.29×2.56mm2，而吞吐量為2.5Gbs功耗為817mW時脈333MHz的一個(2,4)應用於GF(32)規律的非二進位準循環低密度同位檢查碼解碼器，其操作點是錯誤率10-6. 與目前其他研究的成果相比，我們所提出的解碼器擁有最好的解碼能力，在硬體效率以及能量效率上擁有至少7倍以上的優勢。

Non-binary LDPC codes extended from binary LDPC codes have excellent decoding performance and high burst error resistance, and they have lower routing complexity in contrast to binary LDPC codes. However, the challenges are the high computational complexity and huge memory usage for VLSI implementation. In this thesis, a hardware and energy efficient architecture for implementing non-binary LDPC decoder using Improved Trellis Min-Max algorithm is presented. The Improved Trellis Min-Max algorithm has low computational complexity due to it easily hardware sharing, and we significantly enhance the throughput by eliminating the redundant cycles. Benefited by layered scheduling and appropriate code construction, storage elements of the edge message are reduced as well. Furthermore, a stall-free pipeline architecture is proposed to achieve high throughput. Using 90-nm CMOS process technology, a (2,4)-regular non-binary quasi-cyclic (QC) LDPC decoder over GF(32) is implemented with 1063k decoder gate count, while the chip area including testing consideration is 2.29 × 2.56 mm2. From the post-layout simulation results, the decoder throughput can achieve over 2.5 Gbps with 817 mW under 333 MHz clock frequency and bit error rate 10−6. Compared with state-of-the-art designs, this work has not only the best decoding performance but also over 7 times improvement in both hardware efficiency and energy efficiency.